MC68L300EC16/D

17

Figure 13 BDM Serial Communication Timing Diagram

Figure 14 BDM Freeze Assertion Timing Diagram

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

Table 7 Background Debugging Mode Timing

(V

DD

and V

DDSYN

= 3.0 to 3.6Vdc, V

SS

= 0 Vdc, T

A

= T

L

to T

H)

1

Num

Characteristic

Symbol

Min

Max

Unit

B0

DSI Input Setup Time

tDSISU

15

—

ns

B1

DSI Input Hold Time

tDSIH

10

—

ns

B2

DSCLK Setup Time

tDSCSU

15

—

ns

B3

DSCLK Hold Time

tDSCH

10

—

ns

B4

DSO Delay Time

tDSOD

—25

ns

B5

DSCLK Cycle Time

tDSCCYC

2—

tcyc

B6

CLKOUT Low to FREEZE Asserted/Negated

tFRZAN

—50

ns

B7

CLKOUT High to IFETCH High Impedance

tIPZ

—50

ns

B8

CLKOUT High to IFETCH Valid

tIP

—50

ns

B9

DSCLK Low Time

tDSCLO

1—

tcyc

68300 BKGD DBM SER COM TIM

B1

B3

B2

B0

B4

CLKOUT

FREEZE

BKPT/DSCLK

IFETCH/DSI

IPIPE/DSO

B5

B9

68300 BDM FRZ TIM

B8

CLKOUT

FREEZE

IFETCH/DSI

B6

B6

B7

Freescale Semiconductor, Inc.

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