18

MC68L300EC16/D

Figure 15 ECLK Timing Diagram

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.

3. Address access time = tEcyc – tEAD – tEDSR.

4. Chip select access time = tEcyc – tECSD – tEDSR.

Table 8 ECLK Bus Timing

(V

DD

and V

DDSYN

= 3.0 to 3.6Vdc, V

SS

= 0 Vdc, T

A

= T

L

to T

H

)1

Num

Characteristic

Symbol

Min

Max

Unit

E1

ECLK Low to Address Valid2

tEAD

—60

ns

E2

ECLK Low to Address Hold

tEAH

15

—

ns

E3

ECLK Low to CS Valid (CS Delay)

tECSD

—

150

ns

E4

ECLK Low to CS Hold

tECSH

15

—

ns

E5

CS Negated Width

tECSN

30

—

ns

E6

Read Data Setup Time

tEDSR

30

—

ns

E7

Read Data Hold Time

tEDHR

5—

ns

E8

ECLK Low to Data High Impedance

tEDHZ

—60

ns

E9

CS Negated to Data Hold (Read)

tECDH

0—

ns

E10

CS Negated to Data High Impedance

tECDZ

—1

tcyc

E11

ECLK Low to Data Valid (Write)

tEDDW

—2

tcyc

E12

ECLK Low to Data Hold (Write)

tEDHW

15

—

ns

E13

Address Access Time (Read)3

tEACC

386

—

ns

E14

Chip-Select Access Time (Read)4

tEACS

296

—

ns

E15

Address Setup Time

tEAS

1/2

—

tcyc

68300 E CYCLE TIM

CLKOUT

ADDR[23:0]

CS

ECLK

DATA[15:0]

E1

2A

3A

E2

E5

E4

E3

E9

E7

E8

E10

E12

E14

E13

1A

DATA[15:0]

E15

E11

WRITE

READ

WRITE

E6

R/W

Freescale Semiconductor, Inc.

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