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ST72361 데이터시트(PDF) 97 Page - STMicroelectronics |
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ST72361 데이터시트(HTML) 97 Page - STMicroelectronics |
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97 / 224 page ![]() ST72361 97/224 8-BIT TIMER (Cont’d) 10.5.3.3 Output Compare In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 8-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – Assigns pins with a programmable value if the OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 8-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 00h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the fol- lowing in the CR2 register: – Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. – Select the timer clock (CC[1:0]) (see Table 1). And select the following in the CR1 register: – Select the OLVLi bit to applied to the OCMPi pins after the match occurs. – Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: – OCFi bit is set. – The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). – A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: ∆t = Output compare period (in seconds) fCPU = PLL output x2 clock frequency in hertz (or fOSC/2 if PLL is not enabled) PRESC = Timer prescaler factor (2, 4, 8 or 8000 depending on CC[1:0] bits, see Table 1) Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiR register. ∆ OCiR = ∆ t * fCPU PRESC |
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