S71GS256 datasheet(104/195 Pages) SPANSION

104 / 195 page

104

CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

that part of the DRAM array that contains essential data. Temperature compen-

sated refresh (TCR) adjusts the refresh rate to match the device temperature—

the refresh rate decreases at lower temperatures to minimize current consump-

tion during standby. Deep power-down (DPD) enables the system to halt the

refresh operation altogether when no vital information is stored in the device. The

system-configurable refresh mechanisms are accessed through the RCR.

Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di-

agrams for detailed information.

Figure 21. Functional Block Diagram

128M: A[22:0]

64M: A[21:0]

32M: A[20:0]

Input/

Output

MUX

and

Buffers

Control

Logic

DRAM

MEMORY

ARRAY

CE#

WE#

OE#

CLK

ADV#

CRE

WAIT

LB#

UB#

DQ[7:0]

DQ[15:8]

Address Decode

Logic

Refresh Configuration

Bus Configuration

S71GS256 데이터시트(PDF) 104 Page - SPANSION

S71GS256 데이터시트(HTML) 104 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL