Nexperia

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

5. Pinning information

5.1. Pinning

74LVC16374A

74LVCH16374A

001aaa231

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1Q0

1Q1

GND

1D0

1D1

GND

1OE

1CP

1Q2

1Q3

VCC

1Q4

1Q5

GND

1Q6

1Q7

2Q0

2Q1

GND

2Q2

2Q3

VCC

2Q4

2Q5

GND

2Q6

2Q7

2OE

1D2

1D3

VCC

1D4

1D5

GND

1D6

1D7

2D0

2D1

GND

2D2

2D3

VCC

2D4

2D5

GND

2D6

2D7

2CP

Fig. 5. Pin configuration SOT362-1 (TSSOP48)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1OE, 2OE

1, 24

output enable input (active LOW)

GND

4, 10, 15, 21, 28, 34, 39, 45

ground (0 V)

VCC

7, 18, 31, 42

supply voltage

1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7

2, 3, 5, 6, 8, 9, 11, 12

data output

2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7

13, 14, 16, 17, 19, 20, 22, 23

data output

1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7

47, 46, 44, 43, 41, 40, 38, 37

data input

2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7

36, 35, 33, 32, 30, 29, 27, 26

data input

1CP, 2CP

48, 25

clock input

74LVC_LVCH16374A

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Product data sheet

Rev. 13 — 27 September 2021

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