Nexperia

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

-40 °C to +85 °C

-40 °C to +125 °C

Symbol Parameter

Conditions

Min

Typ[1]

Max

Min

Max

Unit

nDn to nCP; see Fig. 8

VCC = 1.65 V to 1.95 V

4.0

-

-

4.0

-

ns

VCC = 2.3 V to 2.7 V

3.0

-

-

3.0

-

ns

VCC = 2.7 V

1.9

-

-

1.9

-

ns

tsu

set-up time

VCC = 3.0 V to 3.6 V

1.9

0.3

-

1.9

-

ns

nDn to nCP; see Fig. 8

VCC = 1.65 V to 1.95 V

3.0

-

-

3.0

-

ns

VCC = 2.3 V to 2.7 V

2.5

-

-

2.5

-

ns

VCC = 2.7 V

1.1

-

-

1.1

-

ns

th

hold time

VCC = 3.0 V to 3.6 V

+1.5

-0.3

-

1.5

-

ns

see Fig. 6

VCC = 1.65 V to 1.95 V

100

-

-

80

-

ns

VCC = 2.3 V to 2.7 V

125

-

-

100

-

ns

VCC = 2.7 V

150

-

-

120

-

MHz

fmax

maximum

frequency

VCC = 3.0 V to 3.6 V

150

300

-

120

-

MHz

tsk(o)

output skew time VCC = 3.0 V to 3.6 V

[3]

-

-

1.0

-

1.5

ns

per input; VI = GND to VCC

[4]

VCC = 1.65 V to 1.95 V

-

14.1

-

-

-

pF

VCC = 2.3 V to 2.7 V

-

16.4

-

-

-

pF

CPD

power

dissipation

capacitance

VCC = 3.0 V to 3.6 V

-

18.5

-

-

-

pF

[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL x VCC 2 x fo) = sum of the outputs

10.1. Waveforms and test circuit

001aaa256

nCP input

nQn output

tPHL

tPLH

tW

VOH

VI

GND

VOL

VM

VM

VM

1/fmax

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig. 6. Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency

74LVC_LVCH16374A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 13 — 27 September 2021

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