Nexperia

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

4. Functional diagram

001aaa253

1Q0

1Q1

1CP

2CP

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1OE

47

46

48

25

44

43

41

40

38

37

2

3

1

5

6

8

9

11

12

24

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

36

35

33

32

30

29

27

26

13

14

16

17

19

20

22

23

2OE

Fig. 1. Logic symbol

23

001aaa254

37

12

11

9

8

6

5

47

46

44

43

41

40

38

1D7

1D0

1D1

1D2

1D3

1D4

1D5

1D6

2

3

1Q7

1Q6

1Q5

1Q4

1Q3

1Q2

1Q0

1Q1

26

22

20

19

17

16

36

35

33

32

30

29

27

2D5

2D0

2D1

2D2

2D3

2D4

13

14

2Q5

2Q4

2Q3

2Q2

2Q1

2Q0

24

25

EN2

1OE

1

EN1

1CP

2OE

2CP

48

C3

C4

3D

1

4D

2D7

2D6

2Q7

2Q6

2

Fig. 2. IEC logic symbol

001aaa255

1CP

1OE

to 7 other channels

D

CP

Q

FF1

1Q0

1D0

2CP

2OE

to 7 other channels

D

CP

Q

FF2

2Q0

2D0

Fig. 3. Logic diagram

to internal circuit

mna705

VCC

data input

Fig. 4. Bus hold circuit

74LVC_LVCH16374A

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 13 — 27 September 2021

2 / 13