MC68340 datasheet(281/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

6- 31

IRQ—Interrupt Request

This bit is the logical OR of the DONE, BES, BED, CONF, and BRKP bits and is cleared

when they are all cleared. IRQ is positioned to allow conditional testing as a signed

binary integer. The state of this bit is not affected by the interrupt enable bits in the

CCR. The STR bit in the CCR cannot be set when this bit is set; all error status bits,

except the BRKP bit, must be cleared before the STR bit can be set.

1 = An interrupt condition has occurred.

0 = An interrupt condition has not occurred.

DONE—DMA Done

1 = The DMA channel has terminated normally.

0 = The DMA channel has not terminated normally. This bit is cleared by writing a

logic one or by a hardware reset. Writing a zero has no effect.

BES—Bus Error on Source

1 = The DMA channel has terminated with a bus error during the read bus cycle.

0 = The DMA channel has not terminated with a bus error during the read bus cycle.

This bit is cleared by writing a logic one or by a hardware reset. Writing a zero

has no effect.

BED—Bus Error on Destination

1 = The DMA channel has terminated with a bus error during the write bus cycle.

0 = The DMA channel has not terminated with a bus error during the write bus cycle.

This bit is cleared by writing a logic one or by a hardware reset. Writing a zero

has no effect.

CONF—Configuration Error

A configuration error results when either the SAR or the DAR contains an address that

does not match the port size specified in the CCR and the BTC register does not match

the larger port size or is zero.

1 = The CCR STR bit is set, and a configuration error is present.

0 = The CCR STR bit is set, and no configuration error exists. This bit is cleared by

writing a logic one or by a hardware reset. Writing a zero has no effect.

BRKP—Breakpoint

1 = The breakpoint signal was set during a DMA transfer.

0 = The breakpoint signal was not set during a DMA transfer. This bit is cleared by

writing a logic one or by a hardware reset. Writing a zero has no effect.

Bits 1, 0—Reserved

NOTE

The CSR is cleared by writing $7C to its location. The DMA

channel cannot be started until the CSR DONE, BES, BED,

CONF and BRKP bits are cleared.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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