MC68340 datasheet(68/441 Pages) FREESCALE

68 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

3- 19

State 4—The MC68340 issues no new control signals during S4.

State 5—The MC68340 negates

AS and DS during S5. It holds the address and data valid

during S5 to provide address hold time for memory systems. R/

W, SIZ1/SIZ0, and FC3–

FC0 also remain valid throughout S5. The external device must keep

DSACK

≈ asserted

until it detects the negation of

AS or DS (whichever it detects first). The device must

negate

DSACK

≈ within approximately one clock period after sensing the negation of AS

DS. DSACK

≈ signals that remain asserted beyond this limit may be prematurely

detected for the next bus cycle.

3.3.3 Read-Modify-Write Cycle

The read-modify-write cycle performs a read, conditionally modifies the data in the

arithmetic logic unit, and may write the data out to memory. In the MC68340, this

operation is indivisible, providing semaphore capabilities for multiprocessor systems.

During the entire read-modify-write sequence, the MC68340 asserts

RMC to indicate that

an indivisible operation is occurring. The MC68340 does not issue a

BG signal in response

to a

BR signal during this operation. Figure 3-9 is an example of a functional timing

diagram of a read-modify-write instruction specified in terms of clock periods.

CLK

A31–A30

FC3–FC0

R/W

SIZ1–SIZ0

DSACKx

D15–D0

READ

WRITE

INDIVISIBLE

CYCLE

RMC

OUT

Figure 3-9. Read-Modify-Write Cycle Timing

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68340 데이터시트(PDF) 68 Page - Freescale Semiconductor, Inc

MC68340 데이터시트(HTML) 68 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL