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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MC68340 데이터시트(PDF) 72 Page - Freescale Semiconductor, Inc |
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MC68340 데이터시트(HTML) 72 Page - Freescale Semiconductor, Inc |
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72 / 441 page  MOTOROLA MC68340 USER’S MANUAL 3- 23 3.4.2 LPSTOP Broadcast Cycle The low power stop (LPSTOP) broadcast cycle is generated by the CPU32 executing the LPSTOP instruction. Since the external bus interface must get a copy of the interrupt mask level from the CPU32, the CPU32 performs a CPU space type 3 write with the mask level encoded on the data bus, as shown in the following figure. The CPU space type 3 cycle waits for the bus to be available, and is shown externally to indicate to external devices that the MC68340 is going into LPSTOP mode. If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT. The SIM40 provides internal DSACK ≈ response to this cycle. For more information on how the SIM40 responds to LPSTOP mode, see Section 4 System Integration Module. 15 14 13 12 11 10 9876543210 ————————————— I2 I1 I0 I2–I0—Interrupt Mask Level The interrupt mask level is encoded on bits 2–0 of the data bus during an LPSTOP broadcast. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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