MC68340 datasheet(182/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

5- 45

5.5.2.2 BUS ERROR. A bus error exception occurs when an assertion of the

BERR signal

is acknowledged. The

BERR signal can be asserted by one of three sources:

1. External logic by assertion of the

BERR input pin

2. Direct assertion of the internal

BERR signal by an internal module

3. Direct assertion of the internal

BERR signal by the on-chip hardware watchdog

after detecting a no-response condition

Bus error exception processing begins when the processor attempts to use information

from an aborted bus cycle.

When the aborted bus cycle is an instruction prefetch, the processor will not initiate

exception processing unless the prefetched information is used. For example, if a branch

instruction flushes an aborted prefetch, that word is not accessed, and no exception

occurs.

When the aborted bus cycle is a data access, the processor initiates exception processing

immediately, except in the case of released operand writes. Released write bus errors are

delayed until the next instruction boundary or until another operand access is attempted.

Exception processing for bus error exceptions follows the regular sequence, but context

preservation is more involved than for other exceptions because a bus exception can be

initiated while an instruction is executing. Several bus error stack format organizations are

utilized to provide additional information regarding the nature of the fault.

First, any register altered by a faulted-instruction EA calculation is restored to its initial

value. Then a special status word (SSW) is placed on the stack. The SSW contains

specific information about the aborted access—size, type of access (read or write), bus

cycle type, and function code. Finally, fault address, bus error exception vector number,

PC value, and a copy of the SR are saved.

If a bus error occurs during exception processing for a bus error, an address error, a reset,

or while the processor is loading stack information during RTE execution, the processor

halts. This simplifies isolation of catastrophic system failure by preventing processor

interaction with stacks and memory. Only assertion of

RESET can restart a halted

processor.

5.5.2.3 ADDRESS ERROR. Address error exceptions occur when the processor attempts

to access an instruction, word operand, or long-word operand at an odd address. The

effect is much the same as an internally generated bus error. The exception processing

sequence is the same as that for bus error, except that the vector number refers to the

address error exception vector.

Address error exception processing begins when the processor attempts to use

information from the aborted bus cycle. If the aborted cycle is a data space access,

exception processing begins when the processor attempts to use the data, except in the

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