| 전자부품 데이터시트 검색엔진 |
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CS43L21 데이터시트(PDF) 51 Page - Cirrus Logic |
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CS43L21 데이터시트(HTML) 51 Page - Cirrus Logic |
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51 / 63 page ![]() DS723A1 51 CS43L21 Limiter Soft Ramp Disable (LIM_SRDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the soft ramp setting. Note: This bit is ignored when the zero-cross function is enabled (i.e. when DAC_SZC[1:0] = ‘01’b or ‘11’b.) Limiter Zero Cross Disable (LIM_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the zero-cross setting. 6.15 Limiter Release Rate Register (Address 1Ah) Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Peak Detect and Limiter Enable (LIMIT_EN) Default: 0 0 - Disabled 1 - Enabled Function: Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by digital attenuation. Note: When the limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits. Peak Signal Limit All Channels (LIMIT_ALL) Default: 1 0 - Individual Channel 1 - Both channel A & B Function: When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the spe- cific channel indicating clipping. The other channels will not be affected. When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both channels in response to any single channel indicating clipping. 7 6 5 432 10 LIMIT_EN LIMIT_ALL RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0 |
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