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CS43L21 데이터시트(PDF) 16 Page - Cirrus Logic

부품명 CS43L21
상세설명  Low Power, Stereo Digital to Analog Converter
PDF  63 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L21 데이터시트(HTML) 16 Page - Cirrus Logic

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16
DS723A1
CS43L21
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Notes:
8.
Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30
on page 60) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
9.
Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL.)
Parameter (Note 8)
Min
Typ
Max
Unit
Frequency Response 10 Hz to 20 kHz
-0.01
-
+0.08
dB
Passband
to -0.05 dB corner
to -3 dB corner
0
0
-
-
0.4780
0.4996
Fs
Fs
StopBand
0.5465
-
-
Fs
StopBand Attenuation (Note 9)
50
-
-
dB
Group Delay
-
10.4/Fs
-
s
De-emphasis Error
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
dB
dB
dB
Parameters
Symbol
Min
Max
Units
RESET pin Low Pulse Width
(Note 10)
1-
ms
MCLK Frequency
1.024
38.4
MHz
MCLK Duty Cycle
(Note 11)
45
55
%
Slave Mode
Input Sample Rate (LRCK)
Quarter-Speed Mode
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
Fs
Fs
Fs
Fs
4
8
4
50
12.5
25
50
100
kHz
kHz
kHz
kHz
LRCK Duty Cycle
45
55
%
SCLK Frequency
1/tP
-64•Fs
Hz
SCLK Duty Cycle
45
55
%
LRCK Setup Time Before SCLK Rising Edge
ts(LK-SK)
40
-
ns
SDIN Setup Time Before SCLK Rising Edge
ts(SD-SK)
20
-
ns
SDIN Hold Time After SCLK Rising Edge
th
20
-
ns



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