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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 61

Power-Down Sequence

Figure 65:

Power-Down Sequence

All external supplies ramp back down to 0 V. Supplies that are shown to be ramping at the same time

may also be ramped down one by one.

Release Hard Reset

This is achieved by changing the RST_N input from ‘0’ to ‘1’.

Assert Hard Reset

This is achieved by changing the RST_N

input from ‘1’ to ‘0’.

Common Upload (1)

Independent of the sensor operation mode, a group of settings referred to as the Common Upload (1)

must be uploaded in the specified order. These settings are provided in a separate file called

CSG14K_common_upload_1.txt, where every line of that file corresponds to a single 8-bit SPI

transaction or a wait statement. The syntax for these commands is detailed below.

Write DATA to ADDRESS

Lines starting with the write keyword indicate SPI write transactions where DATA specifies the value

to be written to ADDRESS.

Read EXPECTED from ADDRESS

Lines starting with the read keyword indicate SPI read transactions where EXPECTED is the value

that should be read from ADDRESS.

Wait TIME

Lines starting with the wait keyword indicate that a minimum time as specified by TIME has to be

respected before moving on to the next instruction. These wait times are necessary for proper settling

in the sensor.

VDD33*

VDD12*

VDDPIX

CSG14K_CSG8K 데이터시트(PDF) 62 Page - ams AG