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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 20

7.1.9

PLL

Various clock frequencies are required internally to operate the sensor. These are derived from a

single input frequency using an on-chip PLL. Through configuration over SPI, a range of input clock

frequencies is supported.

The main internal clocks are:

●

CLK_ADC is the PLL output clock and is used to operate the ADC.

●

CLK_SER is the sub-LVDS output clock (625 MHz for 1.25 Gbit/s).

●

CLK_PIX is the pixel clock and has a ratio of:

●

1:5 of CLK_SER in 10-bit ADC mode

●

1:6 of CLK_SER in 12-bit ADC mode

7.1.10

OTP Memory

A non-volatile, one time programmable memory is included on-chip. This is programmed with unique

identifier and temperature sensor calibration data.

7.2

Operating the Sensor

This section explains how to connect and power the sensor, as well as basic recipes of how to

configure the sensor in a certain operation mode.

7.2.1

Power Supplies

External Power Supplies

To power the sensor, eight externally generated supplies are required as listed in Figure 6. A Figure 6

distinction is made between digital supplies (VDD12, VDD12C, VDD33D, VDD12_PLL) and analog

supplies (VDD33, VDDPIX, VDD45, VSSNEG). Avoid using switching power supplies when possible,

especially for the analog supplies.

Sufficient bulk (at the regulators) and local (at the sensor pins) decoupling is needed, see Figure 13. In

case of multiple pins for the same supply, local decoupling must be foreseen for each pin (e.g. 3

capacitors for the 3 VDDPIX pins). Separate ground planes must be provided to minimize coupling.

For optimal noise performance, it is advised to keep the analog and digital ground nets separated and

connect them together as close as possible to the external supply regulators.

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