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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMPR4925 데이터시트(PDF) 57 Page - Toshiba Semiconductor |
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TMPR4925 데이터시트(HTML) 57 Page - Toshiba Semiconductor |
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57 / 590 page  Chapter 2 Block Diagram 2-3 (13) NDFMC • NAND Flash memory Controller, Supports ECC (Error Correction Code) function (14) RTC • Real Time Clock, 44-bit up-counter (15) EBIF • External Bus Interface, Connects between 20-bit external address bus/32-bit external data bus and SDRAMC/EBUSC (16) CG • Clock Generator, Incorporates an phase-locked loop (PLL) circuit to drive the multiplied clocks, Generates the clocks for each module (17) G-Bus • High-speed bus which is 32-bit bus width within TX4925, Direct connect to TX49/H2 core block (18) IM-Bus • Low-speed bus which is 32-bit bus width within TX4925, Connect to G-Bus via IMB (19) IMB • G-Bus and IM-Bus bridge (20) TEST • Internal diagnostic module |
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