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TMPR4925 데이터시트(PDF) 92 Page - Toshiba Semiconductor |
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TMPR4925 데이터시트(HTML) 92 Page - Toshiba Semiconductor |
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92 / 590 page ![]() Chapter 5 Configuration Register 5-2 5.2 Register Table 5.2.1 lists the configuration registers. Table 5.2.1 Configuration Register Map Reference Offset Address Size in Bits Mnemonic Register Name 5.2.1 0xE000 32 CCFG Chip Configuration Register 5.2.2 0xE004 32 REVID Chip Revision ID Register 5.2.3 0xE008 32 PCFG Pin Configuration Register 5.2.4 0xE00C 32 TOEA Timeout Error Access Address Register 5.2.5 0xE010 32 PDNCTR Power Down Control Register 0xE014 32 (Reserved) 5.2.6 0xE018 32 GARBP GBUS Arbiter Priority Register 0xE01C 32 (Reserved) 5.2.7 0xE020 32 TOCNT Timeout Count Register 5.2.8 0xE024 32 DRQCTR DMA Request Control Register 5.2.9 0xE028 32 CLKCTR Clock Control Register 5.2.10 0xE02C 32 GARBC GBUS Arbiter Control Register 5.2.11 0xE030 32 RAMP Register Address Mapping Register 0xE034 32 (Reserved) Any address not defined in this table is reserved for future use. |
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