TMPR4925 datasheet(128/590 Pages) TOSHIBA

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Chapter 7 External Bus Controller

7-18

Figure 7.3.15 Ready Input Timing (Write Cycle)

7.3.8

Clock Options

External devices connected to the external bus can use the SYSCLK signal as the clock. The

SYSCLK signal clock frequency can be set to one of the following divisions of the internal bus clock

(GBUSCLK): 1/1, 1/2, 1/3, 1/4. The ADDR[4:3] signal is used to set this frequency during reset, and

the setting is reflected in the SYSCLK Division Ratio field (CCFG.SYSSP) of the Chip Configuration

The operation reference clock frequency can be set to one of the following divisions of the internal

bus clock (GBUSCLK) for each channel independent of the SYSCLK signal clock frequency: 1/1, 1/2,

1/3, 1/4. The external signal of the External Bus Controller operates synchronous to this operation

clock. The Bus Speed field (EBCCRn.SP) of the External Bus Channel Control Register sets this

frequency.

Please set the same value as CCFG.SYSSP to EBCCRn.SP when the external device uses the

SYSCLK signal. If these two values do not match, then the channel, the operation reference clock, and

the SYSCLK signal will no longer be synchronous and will not operate properly.

SYSCLK

CE*

ADDR [19:0]

SWE*/BWE*

DATA [31:0]

ACK*/READY

(Input)

3 clocks

4 clocks

Acknowledge Ready

EBCCRn.PWT:WT=2

EBCCRn.SHWT=0

3 clocks

4 clocks

SYSCLK

CE*

ADDR [19:0]

SWE*/BWE*

DATA [31:0]

ACK*/READY

(Input)

Acknowledge Read

EBCCRn.PWT:WT=2

EBCCRn.SHWT=0

Start Ready

Check

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