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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMPR4925 데이터시트(PDF) 137 Page - Toshiba Semiconductor |
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TMPR4925 데이터시트(HTML) 137 Page - Toshiba Semiconductor |
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137 / 590 page  Chapter 7 External Bus Controller 7-27 7.4.2 External Bus Base Address Register (EBBARn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7) Channel 0 can be used as Boot memory. Therefore, the default is set by the Boot signal (see “7.3.2 Global/Boot-up Options”). Channels 1 - 7 have the same register configuration as Channel 0, but they have different defaults than Channel 0. 31 20 19 16 BA[31:20] Reserved R/W :Type 0x1FC(ch0,7)/0x000(ch1~6) : Initial value 15 32 Reserved : Type : Initial value Only in the case of Channel 0 are fields with different defaults in the “Channel 0/Other channel” state. Bits Mnemonic Field Name Description 31:20 BA[31:20] Base Address External Bus Control Base Address (Initial value: 0x1FC/0x000, R/W) A physical address is used to specify the base address. The upper 12 bits [31:20] of the physical address are compared to the value of this field. 19:0 Reserved Figure 7.4.2 External Bus Base Address Register |
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