TMPR4925 datasheet(177/590 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-7

Three clock cycles are required from external assertion of the DMADONE* signal to disabling

of new DMA access. Operation will not stop even if the bus operation in progress is a Single

transfer or a Burst transfer. For example, if the DMADONE* signal is asserted during Read

operation of Dual Address transfer, the corresponding Write bus operation will also be executed.

If the DMADONE* pin is set to become both input and output for channel n

(DMCCRn.DNCTRL = “11”), the DMADONE* signal becomes an open drain signal when the

channel becomes active. When used by this mode, the DMADONE* signal must be pulled up by

an external source. When in this mode, the External DONE Assert bit (DMCSRn.EXTDN) is not

only set when asserted by an external device, but is also set when asserted by the TX4925.

8.3.4

Internal I/O DMA Transfer Mode

Performs DMA with the on-chip Serial I/O Controller and the AC-link Controller. Set the DMA

Channel Control Register (DMCCRn) as follows.

•

DMCCRn.EXTRQ

= 1: I/O DMA Transfer mode

•

DMCCRn.SNGAD

= 0: Dual Address Transfer

Refer to “8.3.8 Dual Address Transfer” and “11.3.6 DMA transfer (Serial I/O Controller)” or

“14.3.6.4 DMA Operation (AC-link Controller)” for more information.

8.3.5

Memory-Memory Copy Mode

It is possible to copy memory from any particular address to any other particular address when in the

Memory-Memory Copy mode.

Set the DMA Channel Control Register (DMCCRn) as follows.

•

DMCCRn.EXTRQ

= 0: Memory Transfer mode

•

DMCCRn.SNGAD

= 0: Dual Address mode

Furthermore, when in the Memory-Memory Copy mode it is possible to set the interval for requesting

ownership of each bus using the Internal Request Delay field (INTRQD) of the DMA Channel Control

Refer to “8.3.8 Dual Address Transfer” for information regarding the setting of other registers.

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