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TMPR4925 데이터시트(PDF) 183 Page - Toshiba Semiconductor |
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TMPR4925 데이터시트(HTML) 183 Page - Toshiba Semiconductor |
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183 / 590 page ![]() Chapter 8 DMA Controller 8-13 Only 4, 0 and 4 can be set on Burst Inhibit bit during Burst transfer. When the Burst Inhibit bit is set, an any multiples of 4 can be set. (Refer to Table 8.3.3) 8.3.8.3 Double Word Byte Swapping When the Reverse Byte bit (REVBYTE) of the DMA Channel Configuration Register (DMCCRn) is set, read word data is written after byte swapping is performed. For example, if the read data is “0x0123_4567”, then the data “0x6745_2301” is written. The Reverse Byte bit can only be set when the REVBYTE column of Table 8.3.3 is set so “0/1” is indicated. |
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