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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMPR4925 데이터시트(PDF) 243 Page - Toshiba Semiconductor |
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TMPR4925 데이터시트(HTML) 243 Page - Toshiba Semiconductor |
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243 / 590 page  Chapter 9 SDRAM Controller 9-15 9.4.2 SDRAM Timing Register (SDCTR) 0x8020 31 29 28 27 26 25 24 23 22 18 17 16 BC ACP PT RCD ACE PDAE RC CASL DRB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type 101 11 1 1 0 0 00000 1 0 : Initial value 15 14 13 12 11 0 DA SWB DIA RP R/W R/W R/W R/W : Type 1 1 11 0x270 : Initial value Bits Mnemonic Field Name Description 31:29 BC Bank Cycle Time Bank Cycle Time (tRC) (Initial value: 101, R/W) Specifies the bank cycle time. (*2) 000: 5 tCK (*1) 100: 9 tCK 001: 6 tCK 101: 10 tCK 010: 7 tCK 110: Reserved 011: 8 tCK 111: Reserved 28:27 ACP Active Command Time Active Command Period (tRAS) (Initial value: 11, R/W) Specifies the active command time. 00: 3 tCK 01: 4 tCK 10: 5 tCK 11: 6 tCK 26 PT Precharge Time Precharge Time (tRP) (Initial value: 1, R/W) Specifies the precharge time. 0: 2 tCK 1: 3 tCK 25 RCD RAS-CAS Delay RAS to CAS Delay (tRCD) (Initial value: 1, R/W) Specifies the RAS - CAS delay. 0: 2 tCK 1: 3 tCK 24 ACE Advanced CKE Advanced CKE enable (Initial value: 0, R/W) Enabling this function makes the timing at which CKE changes one cycle earlier. 0: Disable 1: Enable 23 PDAE Power Down Auto Entry Power Down Auto Entry Enable (Initial value: 0, R/W) Enabling this function makes CKE become “L” while the SDRAMC is in the Idle state. When refresh, memory access, or command execution is performed, CKE automatically becomes “H”, the requested operation is performed, then CKE returns to “L” when the operation is complete. 0: Disable 1: Enable Figure 9.4.2 SDRAM Timing Register (1/2) |
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