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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMPR4925 데이터시트(PDF) 264 Page - Toshiba Semiconductor |
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TMPR4925 데이터시트(HTML) 264 Page - Toshiba Semiconductor |
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264 / 590 page  Chapter 10 PCI Controller 10-2 10.1.4 PCI Arbiter • Supports four external PCI bus masters • Uses the Programmable Fairness algorithm (two levels with different priorities for four round- robin request/grant pairs) • Supports bus parking • Bus master uses the Most Recently Used algorithm • Unused slots and broken masters can be automatically disabled after Power On reset • On-chip arbitration function can be disabled and external arbiter can be used 10.1.5 PDMAC (PCI DMA Controller) • Direct Memory Access (DMA) Controller dedicated to 1-channel PCI • Is possible to transfer data using minimal G-Bus bandwidth • Data can be transferred bidirectionally between the G-Bus and the PCI Bus • Specifying a physical address on the PCI Bus and an address on the G-Bus makes it possible to automatically transfer data between the PCI Bus and the G-Bus • Supports the Chain DMA mode, in which a Descriptor containing chain-shaped addresses and a transfer size is automatically read from memory while DMA transfer continuous • On-chip 16-stage 32-bit data buffer |
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