TMPR4925 datasheet(284/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-22

10.3.12 PCI Boot

Setting the configuration during boot up (ADDR[8:6] = 0x011) makes it possible to set the reset

exception vector address of the TX49/H2 core to PCI Bus address 0xBFC0_0000.

Two windows of the memory space from the G-Bus to the PCI Bus space are used when in the PCI

Boot mode. The defaults of several registers are changed as indicated below.

•

G-Bus base address (G2GBASE):

0x1FC0_0000

•

Space size (G2PM2MASK):

4 MB

•

PCI Bus base address (G2PM2PBASE):

0xBFC0_0000

•

Initiator Memory Space 2 Enable (PCICCFG.G2PM2EN):

•

Bus Master bit (PCISTATUS.BM) [Only when in the Host mode]

•

Target Configuration Access Ready

(PCICSTAUTS.TCAR) [Only when in the Satellite mode]

Also, the on-chip PCI Bus Arbiter cannot be used when the PCI Boot mode is being used while in the

Satellite mode.

10.3.13 Set Configuration Space

In Table 10.5.1, the values for the registers inside the PCI Configuration Space Register that have a

gray background can be rewritten using one of the following method.

10.3.13.1 Set the Configuration Space Using Software Reset

By using the following procedure, it is possible to use the software to set the configuration

space.

(1) Set the value to be loaded in the Configuration Data 0 Register (PCICDATA0), the

Configuration Data 1 Register (PCICDATA1), the Configuration Data 2 Register

(PCICDATA2), and the Configuration Data 3 Register (PCICDATA3).

(2) Clear the Load Configuration Data Register bit (LCFG) of the PCI Controller Configuration

After these processes are complete, please set the Target Configuration Access Ready bit

(PCICCFG.TCAR) of the PCI Controller Configuration Register to be able to accept access to the

PCI Configuration space.

10.3.14 PCI Clock Signal

The configuration setting via ADDR[18] during boot-up determines whether or not the clock from

the on-chip PLL is driven out from the PCI Clock outputs, PCICLK[2:1] and PCICLKIO. When

ADDR[18] is High, PCICLK[2:1] and PCICLKIO are configured as outputs. When ADDR[18] is Low,

PCICLK[2:1] are forced to the High-Z state and PCICLKIO is configured as an input.

When PCICLK[2:1] and PCICLKIO are configured as outputs, the PCFG.PCICLKIOEN bit must not

be cleared. When configured as an output, the PCIC internally feeds back PCICLKIO as a PCI bus

clock

adjust

the

phase

the

clock.

However,

the

PCFG.PCICLKEN[2:1]

and

PCFG.PCICLKIOEN bits are cleared, PCICLK[2:1] and PCICLKIO are held Low respectively. (see

Figure 6.1.1).

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