전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

TMPR4925 데이터시트(PDF) 291 Page - Toshiba Semiconductor

부품명 TMPR4925
상세설명  64-Bit TX System RISC TX49 Family
PDF  590 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4925 데이터시트(HTML) 291 Page - Toshiba Semiconductor

Back Button TMPR4925 Datasheet HTML 287Page - Toshiba Semiconductor TMPR4925 Datasheet HTML 288Page - Toshiba Semiconductor TMPR4925 Datasheet HTML 289Page - Toshiba Semiconductor TMPR4925 Datasheet HTML 290Page - Toshiba Semiconductor TMPR4925 Datasheet HTML 291Page - Toshiba Semiconductor TMPR4925 Datasheet HTML 292Page - Toshiba Semiconductor TMPR4925 Datasheet HTML 293Page - Toshiba Semiconductor TMPR4925 Datasheet HTML 294Page - Toshiba Semiconductor TMPR4925 Datasheet HTML 295Page - Toshiba Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 291 / 590 page
background image
Chapter 10 PCI Controller
10-29
10.4.4
PCI Configuration 1 Register (PCICFG1)
0xD00C
The following fields correspond to the following registers.
BIST field
→ BIST Register of the PCI Configuration Space
Header Type field
→ Header Type Register in the PCI Configuration Space
Latency Timer field
→ Latency Timer Register of the PCI Configuration Space
Cache Line Size field
→ Cache Line Size Register of the PCI Configuration Space.
This register cannot be accessed when the PCI Controller is in the Satellite mode.
31
30
24
23
22
16
BISTC
Reserved
MFUNS
HT
RR
R/L
: Type
0
0
0x00
: Initial value
15
8
7
0
LT
CLS
R/W
R/W
: Type
0x00
0x00
: Initial value
Bits
Mnemonic
Field Name
Description
31
BISTC
BIST Capable
BIST Capable (Fixed value: 0, R)
Indicates that the BIST function is not being supported.
30:24
Reserved
23
MFUNS
Multi-Function
Multi-Function (Fixed value: 0, R)
0: Indicates that the device is a single-function device.
22:16
HT
Header Type
Header Type (Initial value: 0x00, R/L)
Indicates the Header type.
0000000: Header Type 0
It is possible to change to the value that was written to the PCICDATA3 Register
when PCICCFG.LCFG is “1”.
15:8
LT
Latency Timer
Latency Timer (Initial value: 0x00, R/W)
Sets the latency timer value. Specifies the PCI Bus clock count during which to abort
access when the GNT* signal is deasserted during PCI access. Since the lower two
bits are fixed to “0”, cycle counts can only be specified in multiples of 4.
7:0
CLS
Cache Line Size
Cache Line Size (Initial value: 0x00, R/W)
Is used to select the PCI Bus command during a Burst Read transaction. See “10.3.3
Supported PCI Bus Commands)” for more information.
Figure 10.4.4 PCI Configuration 1 Register



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com