Data Sheet G14309EJ2V0DS00

19

µµµµPC1909

In the

µPC1909, when the power supply voltage (VCC) rises but is less than the operation start voltage (VCC(L to H)),

a current of about 100

µA flows as a standby current.

When VCC reaches or exceeds VCC(L to H), the internal reference voltage (VREF) rises and operating current is supplied to

the internal circuits, increasing the circuit current (ICC) to a level of about 12 mA.

In the startup circuit in Figure 4-2, ICC(SB) is supplied via a startup resistor (R2), and when the power MOS FET is turned

on after the

µPC1909 is started up, ICC is supplied from a capacitor (C1) until voltage reaches the auxiliary coil. R2 is

determined using ICC(SB) as follows.

R2

VIN(MIN.)

− VCC(LtoH)(MAX.)

ICC(SB)(MAX.)

+ IREF

If R2 is too small, the loss via R2 during steady operation will be large. The loss via R2 during steady operation (PL(MAX.))

is shown below. In this equation, NZ is the number of turns in the power supply auxiliary coil, NP is the number of turns in

the primary coil, and VF(D1) is the forward direction voltage drop in the diode (D1).

PL(MAX.) =

{(1

− NZ/NP)·VIN(MAX.) + VF(D1)}

R2

2

Note that a film or other capacitor (C2) with good high-frequency characteristics should be connected to prevent a high-

frequency current flowing through the VCC line when the power MOS FET is driven.

To apply a soft start, connect a soft start capacitor (C3) between the DTC1 pin and GND. Using the overcurrent limitation

function of the OC pin allows the duty to be limited on a pulse-by-pulse basis, enabling a more secure soft start.

The time between the startup of the

µPC1909 and the first output of OUT1 (t1) is expressed as follows.

t1 =

−

ln {1

− (1 + R3 / R4)·(VTH(L) / VREF)}

1

+ R3 / R4

C3 · R3

Although VCC drops in the t1 period, C1 is determined so that OUT1 is output while the drop voltage has not fallen to the

operating voltage hysteresis width VH. At this time, because OUT2 is output before OUT1 (refer to 3.1 Startup), C1 must

be set to compensate for the increase in current caused by the output of OUT2. Refer to Figure 3-1. Waveforms at Startup

for the operating waveforms.

C1 >

ICC

+ IREF + IOUT − ICC(R)

· t1

VH

Here, IREF is the current that flows through the resistor with the maximum duty setting connected to the VREF pin, IOUT is

the power MOS FET drive current, and ICC(R) is the current that is supplied from the startup resistor (R2).