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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PI7C8150AND 데이터시트(PDF) 80 Page - Pericom Semiconductor Corporation |
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PI7C8150AND 데이터시트(HTML) 80 Page - Pericom Semiconductor Corporation |
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80 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 80 of 111 APRIL 2006 – Revision 1.1 Bit Function Type Description 27 Signaled Target Abort R/WC Set to 1 (by a target device) whenever a target abort cycle occurs Reset to 0 28 Received Target Abort R/WC Set to 1 (by a master device) whenever transactions are terminated with target aborts Reset to 0 29 Received Master Abort R/WC Set to 1 (by a master) when transactions are terminated with Master Abort Reset to 0 30 Signaled System Error R/WC Set to 1 when P_SERR_L is asserted Reset to 0 31 Detected Parity Error R/WC Set to 1 when address or data parity error is detected on the primary interface Reset to 0 14.1.5 REVISION ID REGISTER – OFFSET 08h Bit Function Type Description 7:0 Revision R/O Indicates revision number of device. Hardwired to 02h 14.1.6 CLASS CODE REGISTER – OFFSET 08h Bit Function Type Description 15:8 Programming Interface R/O Read as 0 to indicate no programming interfaces have been defined for PCI-to-PCI bridges 23:16 Sub-Class Code R/O Read as 04h to indicate device is PCI-to-PCI bridge 31:24 Base Class Code R/O Read as 06h to indicate device is a bridge device 14.1.7 CACHE LINE SIZE REGISTER – OFFSET 0Ch Bit Function Type Description 7:0 Cache Line Size R/W Designates the cache line size for the system and is used when terminating memory write and invalidate transactions and when prefetching memory read transactions. Only cache line sizes (in units of 4-byte) which are a power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, and 10h are valid values). Reset to 0 14.1.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch Bit Function Type Description 15:8 Primary Latency timer R/W This register sets the value for the Master Latency Timer, which starts counting when the master asserts FRAME_L. Reset to 0 06-0057 |
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