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PI7C8150AND 데이터시트(PDF) 97 Page - Pericom Semiconductor Corporation

부품명 PI7C8150AND
상세설명  2-PORT PCI-to-PCI BRIDGE
PDF  111 Pages
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제조업체  PERICOM [Pericom Semiconductor Corporation]
홈페이지  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI7C8150AND 데이터시트(HTML) 97 Page - Pericom Semiconductor Corporation

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PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 97 of 111
APRIL 2006 – Revision 1.1
14.1.53
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
Bit
Function
Type
Description
1:0
Power State
R/W
Indicates the current power state of PI7C8150A. If an
unimplemented power state is written to this register, PI7C8150A
completes the write transaction, ignores the write data, and does not
change the value of the field. Writing a value of D0 when the
previous state was D3 cause a chip reset without asserting
S_RESET_L
00: D0 state
01: not implemented
10: not implemented
11: D3 state
Reset to 0
7:2
Reserved
R/O
Read as 0
8
PME# Enable
R/O
Read as 0 as PI7C8150A does not support the PME# pin.
12:9
Data Select
R/O
Read as 0 as the data register is not implemented.
14:13
Data Scale
R/O
Read as 0 as the data register is not implemented.
15
PME status
R/O
Read as 0 as the PME# pin is not implemented.
14.1.54
CAPABILITY ID REGISTER – OFFSET E4h
Bit
Function
Type
Description
7:0
Capability ID
R/O
00h: Reserved.
01h: PCI Power Management (PCIPM)
02h: Accelerated Graphics Port (AGP)
03h: Vital Product Data (VPD)
04h: Slot Identification (SI)
05h: Message Signaled Interrupts (MSI)
06h: Compact PCI Hot Swap
07h-255h: Reserved
14.1.55
NEXT POINTER REGISTER – OFFSET E4h
Bit
Function
Type
Description
15:8
Next Pointer
R/O
End of pointer (00h)
15
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME_L signal. In a bridge, there are a number
of possibilities. Those possibilities are summarized in the table below:
06-0057



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