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LXT386LE 데이터시트(PDF) 25 Page - Intel Corporation

부품명 LXT386LE
상세설명  QUAD T1/E1/J1 Transceiver
PDF  78 Pages
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제조업체  INTEL [Intel Corporation]
홈페이지  http://www.intel.com
Logo INTEL - Intel Corporation

LXT386LE 데이터시트(HTML) 25 Page - Intel Corporation

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QUAD T1/E1/J1 Transceiver — LXT386
Datasheet
25
3.2.2.1
E1 Mode
One detection mode suitable for both ETSI and ITU is available when the LACS register bits are
cleared to zero. If the LACS register bit is set to one, see errata 10.3 to implement this:
ETSI ETS300233 and G.775 detection
The AIS condition is declared when the received data stream contains less than 3 zeros within a
period of 512 bits.
The AIS condition is cleared when 3 or more zeros within 512 bits are detected.
3.2.2.2
T1 Mode
ANSI T1.231 detection is employed.
The AIS condition is declared when less than 9 zeros are detected in any string of 8192 bits. This
corresponds to a 99.9% ones density over a period of 5.3ms.
The AIS condition is cleared when the received signal contains 9 or more zeros in any string of
8192 bits.
3.2.3
In Service Code Violation Monitoring
In unipolar I/O mode with HDB3/B8ZS decoding, the LXT386 reports bipolar violations on
RNEG/BPV for one RCLK period for every HDB3/B8ZS code violation that is not part of the zero
code substitution rules. In AMI mode, all bipolar violations (two consecutive pulses with the same
polarity) are reported at the BPV output.
3.3
Transmitter
The four low power transmitters of the LXT386 are identical.
Transmit data is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA
in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization. Unipolar I/O
and HDB3/B8ZS/AMI encoding/decoding is selected by pulling TNEG High for more than 16
consecutive TCLK clock cycles. The transmitter samples TPOS/TNEG or TDATA inputs on the
falling edge of TCLK. Refer to the Test Specifications Section for MCLK and TCLK timing
characteristics. If TCLK is not supplied, the transmitter remains powered down and the TTIP/
TRING outputs are held in a High Z state. In addition, fast output tristatability is also available
through the OE pin (all ports) and/or the port’s OEx bit in the Output Enable Register (OER).
Zero suppression is available only in Unipolar Mode. The two zero-suppression types are B8ZS,
used in T1 environments, and HDB3, used in E1 environments. The scheme selected depends on
whether the device is set for T1 or E1 operation (determined by LEN2-0 pulse shaping settings).
The LXT386 also supports AMI line coding/decoding as shown in Figure 6. In Hardware mode,
AMI coding/decoding is selected by the CODEN pin. In host mode, AMI coding/decoding is
selected by bit 4 in the GCR (Global Control Register).



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