| 전자부품 데이터시트 검색엔진 |
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UPD16675AP/W 데이터시트(PDF) 17 Page - Renesas Technology Corp |
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UPD16675AP/W 데이터시트(HTML) 17 Page - Renesas Technology Corp |
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17 / 38 page ![]() 15 µµµµPD16675A 5.3.4 Duty setting The duty is set. 00011 b2 b1 b0 Choices 000: 1/34 duty cycle 001: 1/36 duty cycleNote MSB LSB Note If the duty cycle is 1/36, PCOM1 and PCOM2 are respectively selected for twice the period of the duty (2/36). 5.3.5 Master/slave setting The master/slaves are set. 00111 b2 b1 b0 Choices 000: Master 001: Slave MSB LSB 5.3.6 Blink setting The blinks of the pictograph of the address whose blink data is “1” are controlled. 01000 b2 b1 b0 Choices 000: Blink halt 001: Blink start (Blink frequency = fOSC/32768) 010: Blink start (Blink frequency = fBRINote/2) MSB LSB Note This refers to the frequency of the external clock which is input from the OSCBRI pin. |
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