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UPD17708 데이터시트(PDF) 210 Page - Renesas Technology Corp |
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UPD17708 데이터시트(HTML) 210 Page - Renesas Technology Corp |
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210 / 358 page ![]() 208 µPD17704, 17705, 17707, 17708, 17709 Figure 15-6. Configuration of PWM Data Registers (with 8-bit counter selected) Note This register is multiplexed with timer 3 modulo register. Sets PWM output duty of each pin Data buffer DBF3 DBF2 Name Symbol Address Bit Data DBF1 DBF0 b3 b2 b1 b0 b7 b8 0 b9 0 b10 0 b11 0 b12 0 b13 0 b14 0 b15 0 b6 b5 b4 PWM data register 2Note PWMR2 46H Power-ON reset WDT&SP reset CE reset Clock stop 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Retained Transfer data Valid data 0 x Duty: D = Fixed to “0” FFH 16 bits GET PUT Name Symbol Address Bit Data b3 b2 b1 b0 b7 b8 0 b9 0 b10 0 b11 0 b12 0 b13 0 b14 0 b15 0 b6 b5 b4 PWM data register 1 PWMR1 45H Valid data GET PUT Name Symbol Address Bit Data b3 b2 b1 b0 b7 b8 0 b9 0 b10 0 b11 0 b12 0 b13 0 b14 0 b15 0 b6 b5 b4 PWM data register 0 PWMR0 44H Valid data GET PUT x+0.25 256 × 100 % |
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