UPD17708 datasheet(211/358 Pages) RENESAS

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µPD17704, 17705, 17707, 17708, 17709

15.4.2 PWM duty with 9-bit counter selected

The duty setting block compares the value set to each PWM data register (PWMR2 to PWMR0) with the value of

the basic clock counted by each 9-bit counter. If the value of the PWM data register is greater, the block outputs a

high level. If the value of the PWM data register is less, it outputs a low level.

Where the value set to the PWM data register is “x”, therefore, the duty factor can be calculated by the following

expression.

Duty: D =

x + 0.25

× 100%

512

Remark

0.25 is an offset, and a high level is output even where x = 0.

Data is set to each PWM data register for each pin via data buffer (DBF). However, the same basic clock, PWM

counter, and output frequency must be selected for each pin. This means that each pin cannot output a duty factor

of a different cycle independently of the others.

Because the basic clock frequency is 1.125 or 0.1125 MHz, the frequency and cycle of the output signal can be

calculated as follows.

(1) Where output frequency is 2.2 kHz and basic clock frequency is 1.125 MHz

Frequency: f =

1.125 MHz

= 2.197 kHz

512

Cycle:

T =

512

= 455.11

µs

1.125 MHz

(2) Where output frequency is 220 Hz and basic clock frequency is 0.1125 MHz

Frequency: f =

0.1125 MHz

= 219.73 Hz

512

Cycle:

T =

512

= 4.5511 ms

0.1125 MHz

Because the duty setting register of the PWM data registers and timer 3 modulo register are the same register,

they cannot be used at the same time.

When timer 3 is used, PWM data registers 1 and 0 can be used as 8-bit data latches.

UPD17708 데이터시트(PDF) 211 Page - Renesas Technology Corp

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