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UPD750004 데이터시트(PDF) 39 Page - Renesas Technology Corp |
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UPD750004 데이터시트(HTML) 39 Page - Renesas Technology Corp |
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39 / 86 page ![]() µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 37 Data Sheet U10738EJ3V2DS Table 9-1 Status of the Hardware after a Reset (1/2) Program counter (PC) PSW Stack pointer (SP) Stack bank selection register (SBS) Data memory (RAM) General-purpose registers (X, A, H, L, D, E, B, C) Bank selection register (MBS, RBS) Timer/event counter Timer counter Clock timer Serial interface 4 low-order bits at address 0000H in program memory are set in PC bits 11 to 8, and the data at address 0001H are set in PC bits 7 to 0. 5 low-order bits at address 0000H in program memory are set in PC bits 12 to 8, and the data at address 0001H are set in PC bits 7 to 0. Held 0 0 Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 Held 0 0 Held 4 low-order bits at address 0000H in program memory are set in PC bits 11 to 8, and the data at address 0001H are set in PC bits 7 to 0. 5 low-order bits at address 0000H in program memory are set in PC bits 12 to 8, and the data at address 0001H are set in PC bits 7 to 0. Undefined 0 0 Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 Undefined 0 0 Undefined Generation of a RESET signal during operation Generation of a RESET signal in a standby mode Hardware Carry flag (CY) Skip flags (SK0 to SK2) Interrupt status flags (IST0, IST1) Bank enable flags (MBE, RBE) µPD750004 µPD750006, 750008 Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT flip-flop Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT flip-flop Mode register (WM) Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Basic interval timer/ watchdog timer |
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