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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ES9822PRO 데이터시트(PDF) 51 Page - ESS Technology,Inc |
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ES9822PRO 데이터시트(HTML) 51 Page - ESS Technology,Inc |
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51 / 126 page  0.3 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 51 ES9822 PRO Product Datasheet Register 4: ADC CLOCK CONFIG4 Bits [7] [6:4] [3:2] [1] [0] Default 1'b0 3'd0 2'b00 1'b0 1'b0 Bits Mnemonic Description [7] FORCE_PHASE_CLK_IADC Sets phase of CLK_IADC by PHASE_CLK_IADC. • 1'b0: Auto phase tuning if AUTO_CLK_IADC_PHASE_SYNC is set (default) • 1'b1: Sets phase by PHASE_CLK_IADC [6:4] PHASE_CLK_IADC Sets phase of CLK_IADC relative to SYS_CLK when FORCE_PHASE_CLK_IADC is set. For 48M SYS_CLK and 24M CLK_IADC only. • 3'd0: Phase 0 (default) • 3'd1: Phase 1 • others: Reserved [3:2] RESERVED NA [1] INVERT_SAMPLE_CLOCK_CH2 Inverts ADC Ch2 data sampling clock. • 1'b0: Not inverted (default) • 1'b1: Inverted [0] INVERT_SAMPLE_CLOCK_CH1 Inverts ADC Ch1 data sampling clock. • 1'b0: Not inverted (default) • 1'b1: Inverted |
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