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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ES9822PRO 데이터시트(PDF) 55 Page - ESS Technology,Inc |
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ES9822PRO 데이터시트(HTML) 55 Page - ESS Technology,Inc |
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55 / 126 page  0.3 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 55 ES9822 PRO Product Datasheet Register 8: I2S/TDM MASTER MODE CONFIG Bits [7] [6] [5:4] [3] [2] [1] [0] Default 1'b0 1'b0 2'd0 1'b0 1'b0 1'b0 1'b0 Bits Mnemonic Description [7] MASTER_BCK_DIV1 When enabled, master BCK is I2S/TDM master encoding clock. Otherwise, BCK is less than or equal to (I2S/TDM master encoding clock)/2 (unless when ENABLE_2X_MODE or ENABLE_4X_MODE is set). • 1'b0: BCK is not I2S/TDM master encoding clock (default) • 1'b1: BCK is I2S/TDM master encoding clock [6] MASTER_WS_IDLE Sets the value of master WS when WS is idle. • 1'b0: WS is 0 when idle (default) • 1'b1: WS is 1 when idle [5:4] MASTER_FRAME_LENGTH Selects the bit length in each I2S/TDM channel in master mode. • 2'd0: 32 bit (default) • 2'd2: 16 bit • others: Reserved [3] MASTER_WS_PULSE_MODE When enabled, master WS is a pulse signal instead of a 50% duty cycle signal. The pulse width is 1 BCK cycle. • 1'b0: 50% duty cycle WS signal (default) • 1'b1: Pulse WS signal [2] MASTER_BCK_INVERT Inverts master BCK. • 1'b0: Non-inverted (default) • 1'b1: Inverted [1] MASTER_WS_INVERT Inverts master WS. • 1'b0: Non-inverted (default) • 1'b1: Inverted [0] MASTER_MODE_ENABLE Enables I2S/TDM master mode and generates master BCK and master WS. • 1'b0: Disabled (default) • 1'b1: Enabled |
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