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VSC8541XMV-05 데이터시트(PDF) 41 Page - Microchip Technology |
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VSC8541XMV-05 데이터시트(HTML) 41 Page - Microchip Technology |
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41 / 101 page ![]() Registers VMDS-10513 VSC8541-02 Datasheet Revision 4.1 32 4.2.2 Mode Status The register at address 1 in the device main registers space enables reading the currently enabled mode setting. The following table shows possible readouts of this register. 4.2.3 Device Identification All 16 bits in both register 2 and register 3 in the VSC8541-02 device are used to provide information associated with aspects of the device identification. The following tables list the expected readouts. 1. Before selecting the 1000 Mbps forced speed mode, manually configure the PHY as master or slave by setting bit 11 in register 9 (1000BASE-T Control) and MDI or MDIX by setting bits 3:2 in register 19E1 (Extended Mode Control). Table 22 • Mode Status, Address 1 (0x01) Bit Name Access Description Default 15 100BASE-T4 capability RO 1: 100BASE-T4 capable. 0 14 100BASE-TX FDX capability RO 1: 100BASE-TX FDX capable. 1 13 100BASE-TX HDX capability RO 1: 100BASE-TX HDX capable. 1 12 10BASE-T FDX capability RO 1: 10BASE-T FDX capable. 1 11 10BASE-T HDX capability RO 1: 10BASE-T HDX capable. 1 10 100BASE-T2 FDX capability RO 1: 100BASE-T2 FDX capable. 0 9 100BASE-T2 HDX capability RO 1: 100BASE-T2 HDX capable. 0 8 Extended status enable RO 1: Extended status information present in register 15. 1 7 Reserved RO Reserved. 6 Preamble suppression capability RO 1: MF preamble can be suppressed. 0: MF required. 1 5 Autonegotiation complete RO 1: Auto-negotiation complete. 0 4 Remote fault RO Latches high. 1: Far-end fault detected. 0 3 Autonegotiation capability RO 1: Auto-negotiation capable. 1 2 Link status RO Latches low. 1: Link is up. 0 1 Jabber detect RO Latches high. 1: Jabber condition detected. 0 0 Extended capability RO 1: Extended register capable. 1 Table 23 • Identifier 1, Address 2 (0x02) Bit Name Access Description Default 15:0 Organizationally unique identifier (OUI) RO OUI most significant bits (3:18) 0×0007 Table 24 • Identifier 2, Address 3 (0x03) Bit Name Access Description Default 15:10 OUI RO OUI least significant bits (19:24) 000001 9:4 Microsemi model number RO VSC8541-02 110111 3:0 Device revision number RO Revision C 0010 |
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