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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VSC8541XMV-05 데이터시트(PDF) 92 Page - Microchip Technology |
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VSC8541XMV-05 데이터시트(HTML) 92 Page - Microchip Technology |
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92 / 101 page  Pin Descriptions VMDS-10513 VSC8541-02 Datasheet Revision 4.1 83 R/GMII COL 18 I/O, PD VDDMAC GMII/MII collision output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII CRS 19 I/O, PD VDDMAC GMII/MII carrier sense output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII GTX_CLK 37 I, PD VDDMAC GMII/RGMII transmit clock input R/GMII MII_TXCLK 36 I/O, PD VDDMAC MII transmit clock output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RX_CLK 32 I/O, PD VDDMAC GMII/MII receive clock output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RX_DV/RX_CTL 30 I/O, PD VDDMAC GMII/MII receive data valid output/RGMII receive control output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RX_ER 31 I/O, PD VDDMAC GMII/MII receive data error output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RXD0 29 I/O, PD VDDMAC GMII/MII/RGMII data output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RXD1 27 I/O, PD VDDMAC GMII/MII/RGMII data output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RXD2 26 I/O, PD VDDMAC GMII/MII/RGMII data output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. |
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