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VSC8541XMV-05 데이터시트(PDF) 65 Page - Microchip Technology

부품명 VSC8541XMV-05
상세설명  Single Port Gigabit Ethernet Copper PHY with GMII/RGMII/MII/RMII Interfaces
PDF  101 Pages
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제조업체  MICROCHIP [Microchip Technology]
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VSC8541XMV-05 데이터시트(HTML) 65 Page - Microchip Technology

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Registers
VMDS-10513 VSC8541-02 Datasheet Revision 4.1
56
4.4.11
Extended Interrupt Mask
The following table shows the register settings for the extended interrupt mask at address 28E2.
4.4.12
Extended Interrupt Status
The following table shows the register settings for the extended interrupt status at address 29E2.
7:5
Pad edge rate control
R/W
Sticky bit.
MAC interface edge rate control.
000: Slowest edge rate
001: +1 pad edge rate
010: +2 pad edge rate
011: +3 pad edge rate
100: +4 pad edge rate
101: +5 pad edge rate
110: +6 pad edge rate
111: +7 pad edge rate (fastest)
111
4
RMII CLKOUT enable
R/W
Sticky bit.
0: RMII CLKOUT disabled.
1: RMII CLKOUT enabled.
1
3:1
Reserved
RO
Reserved.
0
MDINT CMOS drive
R/W
Sticky bit.
0: Disabled.
1: Enabled.
0
Table 68 •
Extended Interrupt Mask, Address 28E2 (0x1C)
Bit
Name
Access Description
Default
15:14
Reserved
RO
Reserved.
13
Rx FIFO overflow/underflow interrupt mask
R/W
Sticky bit. 1: Enabled.
0
12
Tx FIFO overflow/underflow interrupt mask
R/W
Sticky bit. 1: Enabled.
0
11:5
Reserved
RO
Reserved.
4
RR switchover complete interrupt mask
R/W
Sticky bit. 1: Enabled.0
3
EEE link fail interrupt mask
R/W
Sticky bit. 1: Enabled.
0
2
EEE Rx TQ timer interrupt mask
R/W
Sticky bit. 1: Enabled.
0
1
EEE wait quiet/Rx TS timer interrupt mask
R/W
Sticky bit. 1: Enabled.
0
0
EEE wake error interrupt mask
R/W
Sticky bit. 1: Enabled.
0
Table 69 •
Extended Interrupt Status, Address 29E2 (0x1D)
Bit
Name
Access Description
Default
15:14
Reserved
RO
Reserved.
13
Rx FIFO overflow/underflow interrupt status
RO
Self-clearing bit.
1: Interrupt pending.
0
12
Tx FIFO overflow/underflow interrupt status
RO
Self-clearing bit.
1: Interrupt pending.
0
11:5
Reserved
RO
Reserved.
Table 67 •
WoL and MAC Interface Control, Address 27E2 (0x1B) (continued)
Bit
Name
Access Description
Default



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