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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8580 데이터시트(PDF) 42 Page - Wolfson Microelectronics plc |
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WM8580 데이터시트(HTML) 42 Page - Wolfson Microelectronics plc |
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42 / 92 page  WM8580 Production Data W PD Rev 4.0 February 2007 42 PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX) The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 21. The clock supplied to this module is selected by the PAIFRXMS_CLKSEL register bits and can be MCLK, PLLACLK, or PLLBCLK. Figure 29 PAIF Receiver Clock Selection REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 PAIF 1 09h 7:6 PAIFRXMS_ CLKSEL 00 PAIF Receiver Master Mode clock source 00 = MCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin Table 36 PAIF Receiver Master Mode Clock Control |
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