WM8580 datasheet(28/92 Pages) WOLFSON

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WM8580

Production Data

PD Rev 4.0 February 2007

1:0

PAIFTXFMT

[1:0]

PAIF Transmitter Audio Data Format

Select

11: DSP Format

10: I2S Format

01: Left justified

00: Right justified

3:2

PAIFTXWL

[1:0]

PAIF Transmitter Audio Data Word

Length

11: 32 bits (see Note 1/2)

10: 24 bits

01: 20 bits

00: 16 bits

PAIFTXLRP

In LJ/RJ/I2S modes

0 = LRCLK not inverted

1 = LRCLK inverted

In DSP Format:

0 = DSP Mode A

1 = DSP Mode B

R13

PAIF 4

0Dh

PAIFTXBCP

PAIF Receiver BCLK polarity

0 = BCLK not inverted

1 = BCLK inverted

1:0

SAIFFMT

[1:0]

SAIF Audio Data Format Select

11: DSP Format

10: I2S Format

01: Left justified

00: Right justified

3:2

SAIFWL

[1:0]

SAIF Audio Data Word Length

11: 32 bits (see Note 1/2)

10: 24 bits

01: 20 bits

00: 16 bits

SAIFLRP

In LJ/RJ/I

2S modes

0 = LRCLK not inverted

1 = LRCLK inverted

In DSP Format:

0 = DSP Mode A

1 = DSP Mode B

SAIFBCP

SAIF BCLK polarity

0 = BCLK not inverted

1 = BCLK inverted

R14

SAIF 2

0Eh

SAIF_EN

SAIF Enable

0 = SAIF disabled

1 = SAIF enabled

Table 16 Audio Interface Control

Notes

Right Justified mode does not support 32-bit data. If word length xAIFxxWL=11b in Right

Justified mode, the word length is forced to 24 bits.

In all modes, the data is signed 2's complement. The digital filters internal signal paths process

24-bit data. If the device is programmed to receive 16 or 20 bit data, the device pads the unused

LSBs with zeros. If the device is programmed into 32 bit mode, the 8 LSBs are ignored.

In 24 bit I2S mode, any data width of 24 bits or less is supported provided that LRCLK is high for

a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles. If exactly 32 bit

clocks occur in one full left/right clock period the interface will auto detect and configure a 16 bit

data word length.

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