WM8580 datasheet(23/92 Pages) WOLFSON

23 / 92 page

Production Data

WM8580

PD Rev 4.0 February 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PAIF 1

09h

2:0

PAIFRX_RATE

[2:0]

010

R10

PAIF 2

0Ah

2:0

PAIFTX_RATE

[2:0]

010

R11

SAIF 1

0Bh

2:0

SAIF_RATE

[2:0]

010

Master Mode MCLK/LRCLK

Ratio:

000 = 128fs

001 = 192fs

010 = 256fs

011 = 384fs

100 = 512fs

101 = 768fs

110 = 1152fs

Table 14 Master Mode RATE Registers

In master mode, the BCLKSEL register controls the number of BCLKs per LRCLK. If the

MCLK:LRCLK ratio is 128fs or 192fs and BCLKSEL = 10, BCLKSEL is overwritten to be 128

BCLKs/LRCLK. Also, if BCLKSEL = 00, and LRCLK is 192fs or 1152fs, the generated BCLK has a

mark-space ratio of 1:2.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PAIF 1

09h

4:3

PAIFRX_BCLKSEL

[1:0]

R10

PAIF 2

0Ah

4:3

PAIFTX_BCLKSEL

[1:0]

R11

SAIF 1

0Bh

4:3

SAIF_BCLKSEL

[1:0]

Master Mode BCLK Rate:

00 = 64 BCLKs/LRCLK

01 = 128 BCLKs/LRCLK

10 = 256 BCLKs/LRCLK

11 = BCLK = System Clock.

Table 15 Master Mode BCLK Control

AUDIO DATA FORMATS

Five popular interface formats are supported:

•

Left Justified mode

•

Right Justified mode

•

I2S mode

•

DSP Mode A

•

DSP Mode B

All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the

exception of 32 bit right justified mode, which is not supported.

Audio Data for each stereo channel is time multiplexed with the interface’s Left-Right-Clock (LRCLK),

indicating whether the left or right channel is present. The LRCLK is also used as a timing reference

to indicate the beginning or end of the data words.

In Left Justified, Right Justified and I2S modes, the minimum number of BCLKs per LRCLK period is

2 times the selected word length. LRCLK must be high for a minimum of BCLK periods equivalent to

the audio word length, and low for minimum of the same number of BCLK periods. Any mark to

space ratio on LRCLK is acceptable provided these requirements are met.

In DSP modes A and B, left and right channels must be time multiplexed and input on the input data

line on the Audio Interface. For the PAIF Receiver, all three left/right DAC channels are multiplexed

on DIN1 (assuming DAC_SEL = 00). LRCLK is used as a frame synchronisation signal to identify the

MSB of the first word. The minimum number of BCLKs per LRCLK period is six times the selected

WM8580 데이터시트(PDF) 23 Page - Wolfson Microelectronics plc

WM8580 데이터시트(HTML) 23 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

데이터시트 다운로드

링크 URL