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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT83SND2CMP3B 데이터시트(PDF) 13 Page - ATMEL Corporation |
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AT83SND2CMP3B 데이터시트(HTML) 13 Page - ATMEL Corporation |
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13 / 241 page  13 4341F–MP3–03/06 AT8xC51SND2C/MP3B 5. Clock Controller The AT8xC51SND2C clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. 5.1 Oscillator The AT8xC51SND2C X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 5-1) that can be configured with off-chip components such as a Pierce oscil- lator (see Figure 5-2). Value of capacitors and crystal characteristics are detailed in the section “DC Characteristics”. The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU core, and a clock for the peripherals as shown in Figure 5-1. These clocks are either enabled or disabled, depending on the power reduction mode as detailed in the section “Power Management” on page 47. The peripheral clock is used to generate the Timer 0, Timer 1, MMC, SPI, and Port sampling clocks. Figure 5-1. Oscillator Block Diagram and Symbol Figure 5-2. Crystal Connection X1 X2 PD PCON.1 IDL PCON.0 Peripheral CPU Core 0 1 X2 CKCON.0 ÷ 2 PER CLOCK Clock Clock Peripheral Clock Symbol CPU CLOCK CPU Core Clock Symbol OSC CLOCK Oscillator Clock Symbol Oscillator Clock VSS X1 X2 Q C1 C2 |
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