AT83SND2CMP3B datasheet(50/241 Pages) ATMEL

50 / 241 page

4341F–MP3–03/06

AT8xC51SND2C/MP3B

10.4.1

Entering Power-down Mode

To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND2C enters the

Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets

PD bit is the last instruction executed.

10.4.2

Exiting Power-down Mode

If VDD was reduced during the Power-down mode, do not exit Power-down mode until VDD is

restored to the normal operating level.

There are 2 ways to exit the Power-down mode:

Generate an enabled external interrupt.

–

The AT8xC51SND2C provides capability to exit from Power-down using INT0, INT1,

and KIN0 inputs. In addition, using KIN input provides high or low level exit capability

(see section “Keyboard Interface”, page 204).

Hardware clears PD bit in PCON register which starts the oscillator and restores the

clocks to the CPU and peripherals. Using INTn input, execution resumes when the

input is released (see Figure 10-3) while using KINx input, execution resumes after

counting 1024 clock ensuring the oscillator is restarted properly (see Figure 10-4).

This behavior is necessary for decoding the key while it is still pressed. In both

cases, execution resumes with the interrupt service routine. Upon completion of the

interrupt service routine, program execution resumes with the instruction

immediately following the instruction that activated Power-down mode.

Note:

1. The external interrupt used to exit Power-down mode must be configured as level sensitive

(

INT0 and INT1) and must be assigned the highest priority. In addition, the duration of the

interrupt must be long enough to allow the oscillator to stabilize. The execution will only

resume when the interrupt is deasserted.

2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM

content.

Figure 10-3. Power-down Exit Waveform Using INT1:0

Figure 10-4. Power-down Exit Waveform Using KIN0

Note:

1. KIN0 can be high or low-level triggered.

Generate a reset.

INT1:0

OSC

Power-down Phase

Oscillator Restart

Active Phase

Active phase

KIN0

OSC

Power-down

1024 clock count

Active phase

AT83SND2CMP3B 데이터시트(PDF) 50 Page - ATMEL Corporation

AT83SND2CMP3B 데이터시트(HTML) 50 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL