AT83SND2CMP3B datasheet(29/241 Pages) ATMEL

29 / 241 page

4341F–MP3–03/06

AT8xC51SND2C/MP3B

7.4

Registers

Table 7-4.

PSW Register

PSW (S:8Eh) – Program Status Word Register

Reset Value = 0000 0000b

Table 7-5.

AUXR Register

AUXR (S:8Eh) – Auxiliary Control Register

543

210

RS1

RS0

Bit Number

Bit

Mnemonic

Description

7CY

Carry Flag

Carry out from bit 1 of ALU operands.

6AC

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

5F0

User Definable Flag 0

4 - 3

RS1:0

Refer to Table 7-1 for bits description.

2OV

Overflow Flag

Overflow set by arithmetic operations.

1F1

User Definable Flag 1

Parity Bit

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

543

210

EXT16

DPHDIS

XRS1

XRS0

EXTRAM

Bit Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6EXT16

External 16-bit Access Enable Bit

Set to enable 16-bit access mode during MOVX instructions.

Clear to disable 16-bit access mode and enable standard 8-bit access mode during

MOVX instructions.

5M0

External Memory Access Stretch Bit

Set to stretch RD or WR signals duration to 15 CPU clock periods.

Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.

DPHDIS

DPH Disable Bit

Set to disable DPH output on P2 when executing MOVX @DPTR instruction.

Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.

3 - 2

XRS1:0

Expanded RAM Size Bits

Refer to Table 7-2 for ERAM size description.

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