AT83SND2CMP3B datasheet(6/241 Pages) ATMEL

6 / 241 page

4341F–MP3–03/06

AT8xC51SND2C/MP3B

4.3

Signals

All the AT8xC51SND2C and AT8XSND2CMP3B signals are detailed by functionality in Table 4-

1 to Table 14.

Table 4-1.

Ports Signal Description

Table 4-2.

Clock Signal Description

Table 4-3.

Timer 0 and Timer 1 Signal Description

Signal

Name

Type

Description

Alternate

Function

P0.7:0

I/O

Port 0

P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written

to them float and can be used as high impedance inputs. To avoid any parasitic

current consumption, floating P0 inputs must be polarized to VDD or VSS.

AD7:0

P2.7:0

I/O

Port 2

P2 is an 8-bit bidirectional I/O port with internal pull-ups.

A15:8

P3.7:0

I/O

Port 3

P3 is an 8-bit bidirectional I/O port with internal pull-ups.

RXD

TXD

INT0

INT1

P4.3:0

I/O

Port 4

P4 is an 8-bit bidirectional I/O port with internal pull-ups.

MISO

MOSI

SCK

Signal

Name

Type

Description

Alternate

Function

Input to the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this pin.

If an external oscillator is used, its output is connected to this pin. X1 is the

clock source for internal timing.

Output of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this pin.

If an external oscillator is used, leave X2 unconnected.

FILT

PLL Low Pass Filter input

FILT receives the RC network of the PLL low pass filter.

Signal

Name

Type

Description

Alternate

Function

INT0

Timer 0 Gate Input

INT0 serves as external run control for timer 0, when selected by GATE0 bit in

TCON register.

External Interrupt 0

INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0

is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low

level on INT0#.

P3.2

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