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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT83SND1CXXX-ROTIL 데이터시트(PDF) 123 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL 데이터시트(HTML) 123 Page - ATMEL Corporation |
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123 / 212 page  123 4109J–8051–10/06 AT8xC51SND1C The interrupt request is generated each time an unmasked flag is set, and the global MMC con- troller interrupt enable bit is set (EMMC in IEN1 register). Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This implies that register content must be saved and tested interrupt flag by interrupt flag to be sure not to forget any interrupts. Figure 15-20. MMC Controller Interrupt System 15.8 Registers Table 102. MMCON0 Register MMCON0 (S:E4h) – MMC Control Register 0 MMC Interface Interrupt Request MCBI MMINT.7 EOCM MMMSK.5 EMMC IEN1.0 MCBM MMMSK.7 EORM MMMSK.6 EOFI MMINT.4 F2FM MMMSK.3 EOFM MMMSK.4 EORI MMINT.6 F2FI MMINT.3 EOCI MMINT.5 F2EM MMMSK.1 F1FM MMMSK.2 F1EI MMINT.0 F1EM MMMSK.0 F1FI MMINT.2 F2EI MMINT.1 7654 3210 DRPTR DTPTR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS Bit Number Bit Mnemonic Description 7DRPTR Data Receive Pointer Reset Bit Set to reset the read pointer of the data FIFO. Clear to release the read pointer of the data FIFO. |
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