AT83SND1CXXX-ROTIL datasheet(124/212 Pages) ATMEL

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124

4109J–8051–10/06

AT8xC51SND1C

Reset Value = 0000 0000b

15.8.0.1

Table 103. MMCON1 Register

MMCON1 (S:E5h) – MMC Control Register 1

Reset Value = 0000 0000b

DTPTR

Data Transmit Pointer Reset Bit

Set to reset the write pointer of the data FIFO.

Clear to release the write pointer of the data FIFO.

5CRPTR

Command Receive Pointer Reset Bit

Set to reset the read pointer of the receive command FIFO.

Clear to release the read pointer of the receive command FIFO.

CTPTR

Command Transmit Pointer Reset Bit

Set to reset the write pointer of the transmit command FIFO.

Clear to release the read pointer of the transmit command FIFO.

3MBLOCK

Multi-block Enable Bit

Set to select multi-block data format.

Clear to select single block data format.

2DFMT

Data Format Bit

Set to select the block-oriented data format.

Clear to select the stream data format.

1RFMT

Response Format Bit

Set to select the 48-bit response format.

Clear to select the 136-bit response format.

CRCDIS

CRC7 Disable Bit

Set to disable the CRC7 computation when receiving a response.

Clear to enable the CRC7 computation when receiving a response.

Bit

Number

Bit

Mnemonic

Description

7654

3210

BLEN3

BLEN2

BLEN1

BLEN0

DATDIR

DATEN

RESPEN

CMDEN

Bit

Number

Bit

Mnemonic

Description

7 - 4

BLEN3:0

Block Length Bits

Refer to Table 101 for bits description. Do not program value > 1011b

3DATDIR

Data Direction Bit

Set to select data transfer from host to card (write mode).

Clear to select data transfer from card to host (read mode).

2DATEN

Data Transmission Enable Bit

Set and clear to enable data transmission immediately or after response has

been received.

RESPEN

Response Enable Bit

Set and clear to enable the reception of a response following a command

transmission.

0CMDEN

Command Transmission Enable Bit

Set and clear to enable transmission of the command FIFO to the card.

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