TSS461C datasheet(7/57 Pages) ATMEL

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TSS461C

4193G–AUTO–12/04

Figure 2. Intel Read and Write Cycles

Motorola Mode

In Motorola mode, the WR pin becomes the R/W command, the RD pin must be con-

nected to ground and the CS pin becomes the E strobe. There is no separate chip select

input. For example, if some external decoder is used, this decoder should not drive the

E input high unless the processors E output is high as well.

See Figure 3 for the Motorola read and write cycles. The main difference between Intel

and Motorola mode is that the timing in Intel mode is referenced to the command signals

(RD and WR), but in Motorola mode the reference is the E signal.

Figure 3. Motorola Read and Write Cycles

Interrupts

If an event occurs in the TSS461C that needs the attention of the processor, this will be

signalled on the active low, open-drain interrupt request pin. The events that create this

request are controlled by the internal registers.

Every time the microprocessor accesses any of the interrupt registers (addresses 0x08

to 0x0B), the INT pin will be released momentarily. This enables the TSS461C to work

with processors that either have edge or level sensitive interrupt inputs.

ALE

AD[7:0]

ADDRESS

DATA TO BE

WRITTEN

ADDRESS

DATA

READ

WRITE CYCLE

READ CYCLE

ALE

AD[7:0]

VSS (RD)

R/W (WR)

E (CS)

ADDRESS

DATA TO BE

WRITTEN

ADDRESS

DATA

READ

WRITE CYCLE

READ CYCLE

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