UJA1069 datasheet(34/64 Pages) PHILIPS

34 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

34 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

[1]

In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is

automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing

the LTC bit under software control.

6.12.10 Special Mode register and Special Mode Feedback register

These registers allow conﬁguration of global SBC parameters during start-up of a system

and allow the settings to be read back.

Read Only

read the register selected by RRS without writing to the

Physical Layer Control register

read the register selected by RRS and write to Physical

Layer Control register

11 to 5

reserved

000 0000 reserved for SBCs with CAN transceiver

LMC

LIN Mode Control

LIN Active mode (in Normal mode and Flash mode only)

LIN Active mode disabled

LSC

LIN Slope Control

up to 10.4 kbit/s (low slope)

up to 20 kbit/s (normal)

LDC

LIN Driver Control

increased LIN driver current capability

LIN driver in conformance with the LIN 2.0 standard

LWEN

LIN Wake-up Enable

wake-up via the LIN-bus enabled

wake-up via the LIN-bus disabled

LTC

LIN Transmitter

Control[1]

LIN transmitter is disabled

LIN transmitter is enabled

Table 11.

Physical Layer Control and Physical Layer Control Feedback register bit description …continued

Bit

Symbol

Description

Value

Function

Table 12.

Special Mode register and Special Mode Feedback register bit description

Bit

Symbol

Description

Value

Function

15 and 14

A1, A0

select Special Mode register

RRS

Read Register Select

read the Interrupt Enable Feedback register

read the Special Mode Feedback register

Read Only

read the register selected by RRS without writing to the

Special Mode register

read the register selected by RRS and write to the

Special Mode register

11 and 10

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

ISDM

Initialize Software

Development Mode[1]

initialization of software development mode

normal watchdog interrupt, reset monitoring and fail-safe

behavior

reserved

reserved for SBCs with CAN transceiver

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

6 and 5

WDPRE [1:0]

Watchdog Prescaler

watchdog prescale factor 1

watchdog prescale factor 1.5

watchdog prescale factor 2.5

watchdog prescale factor 3.5

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