UJA1069 datasheet(33/64 Pages) PHILIPS

33 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

33 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

[1]

RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure

situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached.

[2]

If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status

6.12.9 Physical Layer Control register and Physical Layer Control Feedback

These registers allow conﬁguration of the LIN transceiver of the SBC and allow the

settings to be read back.

Read Only

read register selected by RRS without writing to System

Conﬁguration register

read register selected by RRS and write to System

Conﬁguration register

11 and 10

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

reserved

reserved for SBCs with CAN transceiver

RLC

Reset Length Control

1[1]

tRSTNL long reset lengthening time selected

0tRSTNL short reset lengthening time selected

7 and 6

V3C[1:0]

V3 Control

Cyclic mode 2; tw(CS) long period; see Figure 13

Cyclic mode 1; tw(CS) short period; see Figure 13

continuously ON

OFF

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

V1CMC

V1 Current Monitor

Control

an increasing V1 current causes a reset if the watchdog

was disabled during Standby mode

an increasing V1 current just reactivates the watchdog

during Standby mode, and an interrupt is forced (if enabled)

WEN

Wake Enable[2]

WAKE pin enabled

WAKE pin disabled

WSC

Wake Sample Control

Wake mode cyclic sample

Wake mode continuous sample

ILEN

INH/LIMP Enable

INH/LIMP pin active (See ILC bit)

INH/LIMP pin ﬂoating

ILC

INH/LIMP Control

INH/LIMP pin HIGH if ILEN bit is set

INH/LIMP pin LOW if ILEN bit is set

Table 10.

System Conﬁguration and System Conﬁguration Feedback register bit description …continued

Bit

Symbol

Description

Value

Function

Table 11.

Physical Layer Control and Physical Layer Control Feedback register bit description

Bit

Symbol

Description

Value

Function

15 and 14

A1, A0

select Physical Layer Control register

RRS

Read Register Select

read the General Purpose Feedback register 1

read the Physical Layer Control Feedback register

UJA1069 데이터시트(PDF) 33 Page - NXP Semiconductors

UJA1069 데이터시트(HTML) 33 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

데이터시트 다운로드

링크 URL